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1 fn6425.1 caution: these devices are sensitive to electrostatic discharge ; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) and xdcp are registered trademarks of int ersil americas llc copyright intersil americas llc 2007, 2015. all rights reserved all other trademarks mentioned are the property of their respec tive owners. isl22424 dual digitally controlle d potentiometer (xdcp?) low noise, low power, spi ? bus, 256 taps the isl22424 integrates t wo digitally controlled potentiometers (dcp), control logic and non-volatile memory on a monolithic cmos i ntegrated circuit. the digitally controlled potenti ometers are implemented with a combination of resistor elements and cmos switches. the position of the wiper is controlled by the user through the spi serial interface. each poten tiometer has an associated volatile wiper register (wri) and a non-volatile initial value register (ivri) that can be directly written to and read by the user. the contents of the w ri control the position of the wiper. at power-up the device recalls the contents of the dcps ivri to the corresponding wri. the isl22424 also has 13 gene ral purpose non-volatile registers that can b e used as storage of lookup table for multiple wiper position or any other valuable information. the isl22424 features a dual supply, that is beneficial for applications requiring a bipolar range for dcp terminals between v- and v cc . each dcp can be used as thre e-terminal potentiometer or as two-terminal vari able resistor in a wide variety of applications including control, parameter adjustments, and signal processing. features ? two potentiometers in one package ? 256 resistor taps ? spi serial interface wit h write/read capability ? daisy chain configuration ? shutdown mode ? non-volatile eeprom sto rage of wiper position ? 13 general purpose no n-volatile registers ? high reliability - endurance: 1,000,000 data c hanges per bit per register - register data retention: 50 years @ t ??? 55c ? wiper resistance: 70 ? typical @ 1ma ? standby current <4a max ? shutdown current <4a max ? dual power supply -v cc = 2.25v to 5.5v - v- = -2.25v to -5.5v ?10k ?? 50k ?? or 100k ? total resistance ? extended industrial tempera ture range: -40oc to +125oc ? 14 ld tssop or 16 ld qfn ? pb-free plus anneal pr oduct (rohs compliant) data sheet september 9, 2015
2 fn6425.1 september 9, 2015 ordering information part number (notes 1, 2) part marking resistance option (k ? ) temperature range (c) package (pb-free) pkg. dwg. # isl22424tfv14z (no longer available, recommended replacement: isl22424wfr16z-tk) 22424tfvz 100 -40 to +125 14 ld tssop m14.173 isl22424tfr16z (no longer available, recommended replacement: isl22424wfr16z-tk) 22424tfrz 100 -40 to +125 16 ld qfn l16.4x4a isl22424ufv14z (no longer available, recommended replacement: isl22424wfr16z-tk) 22424ufvz 50 -40 to +125 14 ld tssop m14.173 isl22424ufr16z (no longer available, recommended replacement: isl22424wfr16z-tk) 22424ufrz 50 -40 to +125 16 ld qfn l16.4x4a ISL22424WFV14Z 22424wfvz 10 -40 to +125 14 ld tssop m14.173 isl22424wfr16z 22424wfrz 10 -40 to +125 16 ld qfn l16.4x4a notes: 1. intersil pb-free plus anneal pr oducts employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible wit h both snpb and pb-free solderi ng operations. intersil pb-free products are msl classified at pb-free peak ref low temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 2. add -tk suffix for 1,000 tape and reel option isl22424
3 fn6425.1 september 9, 2015 block diagram spi interface vcc gnd sck sdi sdo cs power up, control and status logic non-volatile registers v- rh0 rl0 rw0 wr0 volatile register and wiper control circuitry rh1 rl1 rw1 wr0 volatile register and wiper control circuitry isl22424 (14 ld tssop) top view isl22424 (16 ld qfn) top view sdo v- cs vcc sck gnd rl1 rw1 rh1 sdi rl0 nc rh0 rw0 1 2 3 4 5 6 7 14 13 12 11 10 9 8 sdo v- cs v cc sck gnd rl1 rw1 rh1 sdi rl0 nc rh0 rw0 nc nc 1 3 4 15 16 14 13 2 12 10 9 11 6 578 isl22424
4 fn6425.1 september 9, 2015 pin descriptions tssop pin qfn pin symbol description 1 11 rh0 high terminal of dcp0 2 12 rl0 low terminal of dcp0 3 13 rw0 wiper terminal of dcp0 4 14 rh1 high terminal of dcp1 5 15 rl1 low terminal of dcp1 6 16 rw1 wiper terminal of dcp1 7 1, 2, 3 nc no connection 8 4 v- negative power supply pin 9 5 sdo data output of the spi serial interface 10 6 sck spi interface clock input 11 7 gnd device ground pin 12 8 sdi data input of the spi serial interface 13 9 cs chip select active low input 14 10 vcc positive power supply pin epad* exposed die pad internally connected to v- * note: pcb thermal land for qfn epad should be connected to v- plane or left floating. for more information refer to http://www.intersil.com/data/tb/tb389.pdf isl22424
5 fn6425.1 september 9, 2015 absolute maximum ratings thermal information storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage at any digital interface pin with respect to gnd . . . . . . . . . . . . . . . . . . . . -0. 3v to v cc +0.3 v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6v to 0.3v voltage at any dcp pin with respect to gnd . . . . . . . . . . v - to v cc i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma latchup . . . . . . . . . . . . . . . . . . . . . . . . . class ii, level a @ +125c esd human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350v thermal resistance (typical, note 3) ? ja (c/w) 14 lead tssop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 16 lead qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 maximum junction temperatur e (plastic package). . . . . . . +1 50c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions temperature range (full industrial) . . . . . . . . . . . .-40 c to +125c power rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mw v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25v to 5.5v v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.25v to -5.5v max wiper current iw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0ma caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 3. ? ja is measured with the component mounted on a high effective the rmal conductivity test board in free air. see tech brief tb379 for details. analog specifications over recommended operating conditi ons unless otherwise stated. symbol parameter test conditions min typ (note 4) max unit r total rhi to rli resistance w option 10 k ? u option 50 k ? t option 100 k ? rhi to rli resistance tolerance -20 +20 % end-to-end temperature coefficient w option 85 ppm/c u, t option 45 ppm/c v rh , v rl dcp terminal voltage v rhi and v rli to gnd v- v cc v r w wiper resistance rh - floating, v rl = v-, force iw current to the wiper, i w = (v cc - v rl )/r total 70 250 ? c h /c l /c w (note 20) potentiometer capacitance see macro model below. 10/10/25 pf i lkgdcp leakage on dcp pins voltage at pin from v- to v cc 0.1 1 a voltage divider mode (v- @ rli; v cc @ rhi; measured at rwi, unloaded) inl (note 9) integral non-linearity w option -1.5 0.5 1.5 lsb (note 5) u, t option -1.0 0.2 1.0 lsb (note 5) dnl (note 8) differential non-linearity monotonic over all tap positions w option -1.0 0.4 1.0 lsb (note 5) u, t option -0.5 0.15 0.5 lsb (note 5) zserror (note 6) zero-scale error w option 0 1 5 lsb (note 5) u, t option 0 0.5 2 fserror (note 7) full-scale error w option -5 -1 0 lsb (note 5) u, t option -2 -1 0 v match (note 10) dcp to dcp matching wipers at the same tap position, the same voltage at all rh terminals and the same voltage at all rl terminals -2 2 lsb (note 5) tc v (note 11, 20) ratiometric temperature coeffici ent dcp register set to 80 hex 4 ppm/c isl22424
6 fn6425.1 september 9, 2015 f cutoff (note 20) -3db cut off frequency wiper at midpoint (80hex) w option (10k) 1 000 khz wiper at midpoint (80hex) u option (50k) 250 khz wiper at midpoint (80hex) t option (100k) 120 khz resistor mode (measurements between r w and r l with r h not connected, or between r w and r h with r l not connected) rinl (note 15) integral non-linearity w option -3 1.5 3 mi (note 12) u, t option -1 0.4 1 mi (note 12) rdnl (note 14) differential non-linearity w option -1.5 0.5 1.5 mi (note 12) u, t option -0.5 0.15 0.5 mi (note 12) roffset (note 13) offset w option 0 1 5 mi (note 12) u, t option 0 0.5 2 mi (note 12) r match (note 16) dcp to dcp matching wipers at the same tap position with the same terminal voltages -2 2 mi (note 12) tc r (note 17, 20) resistance temperature coefficient dcp register set between 32he x and ff hex 40 ppm/c analog specifications over recommended operating conditi ons unless otherwise stated. (continued) symbol parameter test conditions min typ (note 4) max unit operating specifications over the recommended operating conditions unless otherwise spec ified. symbol parameter test conditions min typ (note 4) max unit i cc1 v cc supply current (volatile write/read) v cc = 5.5v, v- = 5.5v, f sck = 5mhz; (for spi active, read and volatile write states only) 0.6 1.0 ma v cc = 2.25v, v- = -2.25v, f sck = 5mhz; (for spi active, read and volatile write states only) 0.25 0.5 ma i v-1 v- supply current (volatile write/read) v- = -5.5v, v cc = 5.5v, f sck = 5mhz; (for spi active, read and volatile write states only) -1.0 -0.3 ma v- = -2.25v, v cc = 2.25v, f sck = 5mhz; (for spi active, read and volatile write states only) -0.5 -0.1 ma i cc2 v cc supply current (non-volatile write/read) v cc = 5.5v, v- = 5.5v, f sck = 5mhz; (for spi active, read and non-volatile write states only) 1.0 2.0 ma v cc = 2.25v, v- = -2.25v, f sck = 5mhz; (for spi active, read and non-volatile write states only) 0.3 1.0 ma i v-2 v- supply current (non-volatile write/read) v- = -5.5v, v cc = 5.5v, f sck = 5mhz; (for spi active, read and non-volatile write states only) -2.0 -1.2 ma v- supply current (non-volatile write/read) v- = -2.25v, v cc = 2.25v, f sck = 5mhz; (for spi active, read and non-volatile write states only) -1.0 -0.4 ma i sb v cc current (standby) v cc = +5.5v, v- = -5.5v @ +85c, spi interface in standby state 0.5 2.0 a v cc = +5.5v, v- = -5.5v @ +125c, spi interface in standby state 1.0 4.0 a v cc = +2.25v, v- = -2.25v @ +85c, spi interface in standby state 0.2 1.0 a v cc = +2.25v, v- = -2.25v @ +125c, spi interface in standby state 0.5 2.0 a isl22424
7 fn6425.1 september 9, 2015 i v-sb v- current (standby) v- = -5.5v, v cc = +5.5v @ +85c, spi interface in standby state -3.0 -0.7 a v- = -5.5v, v cc = +5.5v @ +125c, spi interface in standby state -5.0 -1.5 a v- = -2.25v, v cc = +2.25v @ +85c, spi interface in standby state -2.0 -0.3 a v- = -2.25v, v cc = +2.25v @ +125c, spi interface in standby state -3.0 -0.4 a i sd v cc current (shutdown) v cc = +5.5v, v- = -5.5v @ +85c, spi interface in standby state 0.5 2.0 a v cc = +5.5v, v- = -5.5v @ +125c, spi interface in standby state 1.0 4.0 a v cc = +2.25v, v- = -2.25v @ +85c, spi interface in standby state 0.2 1.0 a v cc = +2.25v, v- = -2.25v @ +125c, spi interface in standby state 0.5 2.0 a i v-sd v- current (shutdown) v- = -5.5v, v cc = +5.5v @ +85c, spi interface in standby state -3.0 -0.7 a v- = -5.5v, v cc = +5.5v @ +125c, spi interface in standby state -5.0 -1.5 a v- = -2.25v, v cc = +2.25v @ +85c, spi interface in standby state -2.0 -0.3 a v- = -2.25v, v cc = +2.25v @ +125c, spi interface in standby state -3.0 -0.4 a i lkgdig leakage current, at pins sck, sdi, sdo and cs voltage at pin from gnd to v cc -1 1 a t wrt (note 20) dcp wiper response time cs rising edge to wiper new position 1.5 s t shdnrec (note 20) dcp recall time from shutdown mode cs rising edge to wiper stored position and rh connection 1.5 s vpor power-on recall voltage minimum vcc at which memory recall o ccurs 1.9 2.1 v vccramp v cc ramp rate 0.2 v/ms t d power-up delay v cc above vpor, to dcp initial value register recall completed, and spi interface in standby state 5ms eeprom specification eeprom endurance 1,000,000 cycles eeprom retention temperature t ?? +55oc 50 years t wc (note 18) non-volatile write cycle time 12 20 ms serial interface specifications v il sck, sdi, and cs input buffer low voltage 0.3 * v cc v v ih sck, sdi, and cs input buffer high voltage 0.7 * v cc v hysteresis sck, sdi, and cs input buffer hysteresis 0.05 * v cc v v ol sdo output buffer low voltage i ol = 4ma for open drain output, pull-up voltage vpu = vcc 00.4v r pu (note 19) sdo pull-up resistor off-chip maximum is determined by t ro and t fo with maximum bus load cb = 30pf, f sck = 5mhz 2k ? operating specifications over the recommended operating c onditions unless otherwise spec ified. (continued) symbol parameter test conditions min typ (note 4) max unit isl22424
8 fn6425.1 september 9, 2015 cpin (note 20) sck, sdi, sdo and cs pin capacitance 10 pf f sck spi frequency 5mhz t cyc spi clock cycle time 200 ns t wh spi clock high time 100 ns t wl spi clock low time 100 ns t lead lead time 250 ns t lag lag time 250 ns t su sdi, sck and cs input setup time 50 ns t h sdi, sck and cs input hold time 50 ns t ri sdi, sck and cs input rise time 10 ns t fi sdi, sck and cs input fall time 10 20 ns t dis sdo output disable time 0 100 ns t so sdo output setup time 50 ns t v sdo output valid time 150 ns t ho sdo output hold time 0 ns t ro sdo output rise time r pu = 2k, cbus = 30pf 60 ns t fo sdo output fall time r pu = 2k, cbus = 30pf 60 ns t cs cs deselect time 2s notes: 4. typical values are for t a = +25c and 3.3v supply voltage. 5. lsb: [v(rw) 255 C v(rw) 0 ] / 255. v(rw) 255 and v(rw) 0 are v(rw) for the dcp register set to ff hex and 00 hex respec tively. lsb is the incremental voltage when changing from one tap to an adjacent t ap. 6. zs error = v(rw) 0 / lsb. 7. fs error = [v(rw) 255 C v cc ] / lsb. 8. dnl = [v(rw) i C v(rw) i-1 ] / lsb-1, for i = 1 to 255. i is the dcp register setting. 9. inl = [v(rw) i C i ? lsb C v(rw)]/lsb for i = 1 to 255. 10. v match = [v(rwx)i -v(rwy)i]/lsb, for i = 0 to 255, x = 0 to 1, y = 0 t o 1. 11. for i = 16 to 240 decimal, t = -40c to +125c. max( ) is th e maximum value of the wiper voltage and min ( ) is the minimum value of the wiper voltage o ver the temperature range. 12. mi = | rw 255 C rw 0 | / 255. mi is a minimum increment. rw 255 and rw 0 are the measured resistances for the dcp register set to ff he x and 00 hex respectively. 13. roffset = rw 0 / mi, when measuring between rw and rl. roffset = rw 255 / mi, when measuring between rw and rh. 14. rdnl = (rw i C rw i-1 ) / mi -1, for i = 1 to 255. 15. rinl = [rw i C (mi ? i) C rw 0 ] / mi, for i = 1 to 255. 16. r match = [(rx)i -(ry)i]/mi, for i = 0 to 255, x = 0 to 1, y = 0 to 1. 17. for i = 16 to 240, t = -40c to +125c. max( ) is the maximu m value of the resistance and min ( ) is the minimum value of the resistance over the temperature range. 18. t wc is the time from the end of a write sequence of spi serial int erface, to the end of the self-timed internal non-volatile writ e cycle. 19. r pu is specified for the highest d ata rate transfer for the device . higher value pull-up can be used at lower data rates. 20. this parameter is not 100% tested. operating specifications over the recommended operating c onditions unless otherwise spec ified. (continued) symbol parameter test conditions min typ (note 4) max unit tc v max v rw ?? i ?? min v rw ?? i ?? C max v rw ?? i ?? min v rw ?? i ?? + ?? 2 ? --------------------------------------------------------------- ------------------------------ - 10 6 165c ---------------- - ? = + tc r max ri ?? min ri ?? C ?? max ri ?? min ri ?? + ?? 2 ? --------------------------------------------------------------- - 10 6 165c ---------------- - ? = + isl22424
9 fn6425.1 september 9, 2015 dcp macro model timing diagrams input timing output timing xdcp timing (for all load instructions) 10pf rh r total c h 25pf c w c l 10pf rw rl ... cs sck sdi sdo msb lsb high impedance t lead t h t su t fi t cs t lag t cyc t wl ... t ri t wh ... cs sck sdo sdi addr msb lsb t dis t ho t v ... t so ... cs sck sdi msb lsb v w t wrt ... sdo high impedance
10 fn6425.1 september 9, 2015 typical performance curves figure 1. wiper resistance vs tap position [ i(rw) = v cc /r total ] for 10k ? (w) figure 2. standby i cc and i v- vs temperature figure 3. dnl vs tap position in voltage divider mode for 10k ? (w) figure 4. inl vs tap position in voltage divider mode for 10k ? (w) figure 5. zs error vs temperature figure 6. fs error vs temperature 0 10 20 30 40 50 60 70 80 0 50 100 150 200 250 tap position (decimal) wiper resistance ( ? ) t = +25oc t = -40oc t = +125oc -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -40 0 40 80 120 temperature (c) standby current (a) i cc i v- -0.50 -0.25 0 0.25 0.50 0 50 100 150 200 250 tap position (decimal) dnl (lsb) t = +25oc v cc = 2.25v v cc = 5.5v -0.50 -0.25 0 0.25 0.50 0 50 100 150 200 250 tap position (decimal) inl (lsb) t = +25oc v cc = 5.5v v cc = 2.25v 0 0.4 0.8 1.2 1.6 2.0 -40 0 40 80 120 temperature (oc) zs error (lsb) v cc = 2.25v v cc = 5.5v 50k 10k -5 -4 -3 -2 -1 0 -40 0 40 80 120 temperature (oc) fs error (lsb) v cc = 5.5v 10k 50k v cc = 2.25v isl22424
11 fn6425.1 september 9, 2015 figure 7. dnl vs tap position in rheostat mode for 10k ? (w) figure 8. inl vs tap position in rheostat mode for 10k ? (w) figure 9. end to end r total % change vs temperature figure 10. tc for voltage divider mode in ppm figure 11. tc for rheostat mode in ppm figure 12. frequency response (1mhz) typical performance curves (continued) -0.50 -0.25 0 0.25 0.5 0 50 100 150 200 250 tap position (decimal) rdnl (mi) v cc = 2.25v v cc = 5.5v t = +25oc -0.5 0 0.5 1.0 1.5 2.0 0 50 100 150 200 250 tap position (decimal) rinl (mi) v cc = 5.5v t = +25oc v cc = 2.25v -0.40 0.00 0.40 0.80 1.20 1.60 -40 0 40 80 120 r total change (%) 10k 50k 5.5v 2.25v temperature (oc) 0 40 80 120 160 200 16 66 116 166 tap position (decimal) tcv (ppm/oc) 50k 10k 216 266 0 100 200 300 400 500 16 66 116 166 216 tap position (decimal) tcr (ppm/oc) 50k 10k output input wiper at mid point (position 80h) r total = 10k ? isl22424
12 fn6425.1 september 9, 2015 pin description potentiometer pins rhi and rli the high (rhi) and low (rli) terminals of the isl22424 are equivalent to the fixed terminals of a mechanical potentiometer . rhi and rli are referenced to t he relative position of the wipe r and not the voltage pot ential on the termina ls. with wri set to 255 decimal, the wiper will be cl osest to rhi, and with the wri set to 0, the wiper i s closest to rli. rwi rwi is the wiper terminal and is equivalent to the movable terminal of a mechanical potenti ometer. the position of the wiper within the array is det ermined by the wri register. bus interface pins serial clock (sck) this is the serial c lock input of the spi serial interface. serial data output (sdo) the sdo is a serial data output pin. during a read cycle, the data bits are shifted out on the falling edge of the serial clo ck sck and will be available to the master on the following rising edge of sck. the output type is configured t hrough acr[1] bit for push - pull or open drain oper ation. default setting for this pin is push - pull. an external pull up resistor is required for open drain output operatio n. note: the external pull up voltage not allowed beyond v cc . serial data input (sdi) the sdi is the serial data input pin for the spi interface. it receives device address, operation code, wiper address and data from the spi remote host device. the data bits are shifted in at the rising edge of the serial clock sck, while th e cs input is low. chip select (cs ) cs low enables the isl22424, placing it in the active power mode. a high to low transition on cs is required prior to the start of any operation after power up. when cs is high, the isl22424 is deselected and the sdo pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. principles of operation the isl22424 is an integrated circuit incorporating two dcps with their associated reg isters, non-volatile memory and the spi serial interface pr oviding direct communication between host, potentiometers and memory. the resistor arrays are comprised of individual resistors connected in a series. at either end of the arra y and between e ach resistor is an electronic swit ch that transfers t he potential at that point to the wiper. the electronic switches on the device operat e in a make before break mode when the w iper changes tap positions. when the device is powered dow n, the last value stored in ivri will be maintained in the non-volatile memory. when power is restored, the content of the ivri is recalled and loaded into the corresponding wri to set the wiper to the initial position. dcp description each dcp is implemented with a combination of resistor elements and cmos switc hes. the physical ends of each dcp are equivalent to the fix ed terminals of a mechanical potentiometer (rhi and rli pin s). the rwi pin of the dcp is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. the position of the wiper terminal within the dc p is controlled by an 8-bit volatile wiper register (w ri). when the wri of a dcp figure 13. midscale glitch, code 7fh to 80h figure 14. large signal settling time typical performance curves (continued) scl wiper cs wiper unloaded, movement from 0h to ffh isl22424
13 fn6425.1 september 9, 2015 contains all zeroes (wri[7:0]= 00h), its wiper terminal (rwi) i s closest to its low terminal (rl i). when the wri register of a dcp contains all ones (wri[7:0] = ffh), its wiper terminal (rwi) is closest to its high terminal (rhi). as the value of the wri increases from all zeroes ( 0) to all ones (255 decimal), the wiper moves monotonically fr om the position closest to rli to the closest to rhi. at t he same time, the resistance between rwi and rli increases monotonically, while the resistance between rhi and rwi decreases monotonically. while the isl22424 is being powered up, the wri is reset to 80h (128 decimal), which locat es rwi roughly at the center between rli and rhi. after the power supply voltage becomes large enough for reliable non-volatile memory reading, the wri will be reloaded with the value stored in a corresponding non-volatile init ial value register (ivri). the wri and ivri can be read or written to directly using the spi serial interface as described in the following sections. memory description the isl22424 contains two non-volatile 8-bit initial value registers (ivri), thirteen non-vo latile 8-bit general purpose (gp) registers, two volatile 8- bit wiper regist ers (wri), and volatile 8-bit access control register (acr). the memory map of isl22424 is in table 1. the non-volatile registers (ivri ) at address 0 and 1, contain initial wiper position and vola tile registers (wri) contain current wiper position. the register at address 0fh is a read-only reserved register. information read from this r egister should be ignored. the non-volatile i vri and volatile w ri registers are accessible with th e same address. the access control register (acr) contains information and control bits descri bed below in table 2. the vol bit (acr[7] ) determines whethe r the access to wiper registers wri or initi al value registers ivri. if vol bit is 0, the non-vola tile ivri and general purpose registers are accessible. if vol bit is 1, only the volatile wr i are accessible. note: value that is written to ivri register also is written to the corresponding wri. the default value of this bit is 0. the shdn bit (acr[6]) disables or enables shutdown mode. when this bit is 0, dcp is in shutdown mode, i.e. each dcp is forced to end-to-end open circuit and rwi is shorted to rli as shown on f igure 15. default value of shdn bit is 1. setting shdn bit to 1 is returned wipers to prior to shutdown mode position. the wip bit (acr[5]) is a read-onl y bit. it indicates that non- volatile write operation is in progress. the wip bit can be read repeatedly after a non-vola tile write to determine if the write has been completed. it is impossible to write or read to the wri or acr while wip bit is 1. the sdo bit (acr[1]) configures type of sdo output pin. the default value of sdo bit is 0 for push - pull output. sdo pin can be configured as ope n drain output for some application. in this case, an external pull up resistor is required. see applications information on page 15. spi serial interface the isl22424 supports an spi ser ial protocol, mode 0. the device is accessed via the s di input and sdo output with data clocked in on the rising edge of sck, and clocked out on the falling edge of sck. cs must be low during communication with the isl22424. sck and cs lines are table 1. memory map address (hex) non-volatile volatile 10 n/a acr f reserved e general purpose n/a d general purpose n/a c general purpose n/a b general purpose n/a a general purpose n/a 9 general purpose n/a 8 general purpose n/a 7 general purpose n/a 6 general purpose n/a 5 general purpose n/a 4 general purpose n/a 3 general purpose n/a 2 general purpose n/a 1ivr1 wr1 0ivr0 wr0 table 2. access control register (acr) bit # 7654321 0 bit name vol shdn wip 0 0 0 sdo 0 rli rwi rhi figure 15. dcp connection in shutdown mode isl22424
14 fn6425.1 september 9, 2015 controlled by the host or master. the isl22424 operates only as a slave device. all communication over the sp i interface is conducted by sending the msb of eac h byte of data first. protocol conventions the spi protocol contains instr uction byte followed by one or more data bytes. a valid instruction byte contains instruction as the three msbs, with the following five register address bits (see table 3). the next byte sent to the i sl22424 is the data byte. table 3. instruction byte format table 4 contains a valid instruction set for isl22424. there are only sixteen register addresses possible for this dcp. if the [r4:r0] bits are 00000 or 00001, then the read or write is to either t he ivri or the wri r egisters (depends of vol bit at acr). if the [r 4:r0] are 10000, then the operation is on the acr. write operation a write operation to the isl2 2424 is a two or more bytes operation. first, it requires, the cs transition from high to low. then host must s end a valid instruc tion byte followed by one or more data bytes to s di pin. the host terminates the write operation by pulling the cs pin from low to high. instruction is execut ed on rising edge of cs . for a write-to address 0 or 1, the msb of t he byte at address 10h (acr[7]) determines if the data byte is to be written to volatile or bot h volatile and non-volatile r egisters. refer to memory description and figure 16. note : the internal non-volatile write cycle starts with the rising edge of cs and requires up to 20ms. during non-volatile write cycle the read operation to acr register is allo wed to check wip bit. read operation a read operation to the isl22424 is a four byte operation. it requires first, the cs transition from high to low. then the host must send a valid instruction byte followed by dummy data byte, a nop instruction byte and another dummy data byte to sdi pin. the spi h ost receives the instruction byte (instruction code + register add ress) and requested data byte from sdo pin on ri sing edge of sck during third and fourth bytes respectively. t he host terminates the read operation by pulling the cs pin from low to high (see figure 17). reading from the ivri will not change the wri, if its contents are different. bit # 76543210 i2 i1 i0 r4 r3 r2 r1 r0 table 4. instruction set instruction set operation i2 i1 i0 r4 r3 r2 r1 r0 0 0 0xxxxxnop 0 0 1xxxxxacr read 0 1 1xxxxxacr write 1 0 0 r4 r3 r2 r1 r0 wr, ivr, gp or acr read 1 1 0 r4 r3 r2 r1 r0 wr, ivr, gp or acr write where x means do not care. figure 16. two byte write sequence cs sck sdi sdo wr instruction data byte 1 3 4 5 7 8 9 10111213141516 26 addr isl22424
15 fn6425.1 september 9, 2015 applications information communicating with isl22424 communication with isl22424 proceeds using spi interface through the acr (address 1000 0b), ivri (address 00000b, 00001b), wri (addresses 000 00b, 00001b) and general purpose registers (addresse s from 00010b to 01110b). the wiper position of each poten tiometer is controlled by the corresponding wri register. wr ites and reads can be made directly to these registers to control and monitor the wiper position without any non-volat ile memory changes. this is done by setting msb bit at address 10000b to 1 (acr[7] = 1). the non-volatile ivri stores t he power up pos ition of the wiper. ivri is accessible when msb bit at address 10000b is set to 0 (acr[7] = 0). writing a new value to the ivri register will set a new power up position for the wiper. also, writing t o this registers will load the same value into the corresponding wri as the ivri. reading from the ivri will no t change the wri, if its contents are different. daisy chain co nfiguration when application needs mo re then one isl22424, it can communicate with all of t hem without additional cs lines by daisy chaining the dcps as shown on figure 18. in daisy chain configuration the sdo pi n of previous chip is connected to sdi pin of the following chip, and each cs and sck pins are connected to the corresponding microcontroller pins in parallel , like regular spi interface imp lementation. the daisy chain configuration can al so be used for simultaneous setting of multiple dcps. note, the num ber of daisy chained dcps is limited only by the driving capabilities of sck and cs pins of microcontroller; for larger num ber of spi devices buffering of sck and cs lines is required. daisy chain write operation the write operation starts by high to lo w transition on cs line, followed by n two bytes wr ite instructions on sdi line with reversed chain access sequen ce: the instruction byte + data byte for the last dcp in chain is going first, as shown on figure 19. the serial data is going through dcps from dcp0 to dcp(n-1) as follow: dcp0 --> dcp1 --> dcp2 --> ... --> dcp(n-1). the write instructi on is executed on the rising edge of cs for all n dcps simultaneously. daisy chain read operation the read operation consists of two parts: first, send read instructions (n two bytes op eration) with valid address; second, read the requested data while sending nop instructions (n two bytes oper ation) as show n on figure 20 and figure 21. the first part starts by high to low transition on cs line, followed by n two bytes read instruction on sdi line with reversed chain access sequence: the instruction byte + dummy data byte for t he last dcp in chai n is going first, followed by low to high transition on cs line. the read instructions are executed during second part of read sequence. it also starts by high to low transition on cs line, followed by n two bytes no p instructions on sdi line and low to high transition of cs . the data is read on every even byte du ring second part of read sequence while every odd byte contains instr uction code + address from which the data is being read. wiper transition when stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients, or overshoot/undershoot, resulting from the sudden transition from a very low impedance make to a much higher impedance break within an extremely short period of time (<50ns). two such code transitions are efh to f0h, and 0fh to 10h. note, that all switch ing transients will settle well within the settling time as stated on the datasheet . a small capacitor can be a dded externally to reduce the amplitude of these voltage tr ansients, but that will also reduce the useful bandwidth of the circuit, thus may not be a good solution for some applicat ions. it may be a good idea, in that case, to use fast amplifi ers in a signal chain for fast recovery. figure 17. four byte read sequence cs sck sdi sdo rd addr nop rd addr read data 1 8 16 24 32 isl22424
16 fn6425.1 september 9, 2015 application example figure 22 shows an example of using isl22424 for gain setting and offset correction in high side current measurement application. d cp0 applies a programmable offset voltage of 25mv to the fb+ pin of the instrumentation amplifier el8173 to adjust outpu t offset to zero voltages. dcp1 programs the gain of t he el8173 from 90 to 110 with 5v output for 10a current th rough current sense resistor. more application exampl es can be found at http://www.intersil. com/data/an/an1145.pdf cs sck mosi miso cs sck sdi sdo cs sck sdi sdo cs sck sdi sdo cs sck sdi sdo c dcp0 dcp1 dcp2 dcp(n-1) figure 18. daisy chain configuration n dcp in a chain cs sck sdi sdo 0 wr d c p2 wr d c p1 wr d c p0 wr d c p1 sdo 1 wr d c p2 sdo 2 wr d c p2 figure 19. daisy chain write sequence of n = 3 dcp 16 clkls 16 clks 16 clks figure 20. two byte operation cs sck sdi sdo instruction addr data in data out 1 2 10 11 12 13 14 15 16 345 67 8 9 isl22424
17 fn6425.1 september 9, 2015 cs sck sdi sdo rd dcp1 rd dcp0 nop nop nop dcp2 out dcp1 out dcp0 out rd dcp2 16 clks 16 clks 16 clks 16 clks 16 clks 16 clks figure 21. daisy chain read sequence of n = 3 dcp rl0 rw0 rh0 in+ in- fb+ fb- v out r 4 150k, 1% r 6 1.37k, 1% v out = 0v to + 5v to adc el8173 is 0.005 ? dc/dc converter output processor load 10a, max 2 3 4 5 6 7 v s - v s + +5v 8 programmable gain 90 to 110 en 1 10k 10k 0.1f 1.2v r 5 309, 1% 50k dcp1 (1/2 isl22424u) +5v -5v r 1 50k, 1% r 3 50k, 1% r 2 1k, 1% dcp0 (1/2 isl22424u) rl1 rh1 rw1 50k figure 22. current sensing with gain and offset control programmable offset 25mv isl22424ufv14z rh0 rl0 rw0 rh1 rl1 rw1 vcc scl sdi gnd sdo cs nc v- +5v -5v 14 10 9 12 13 7 11 8 6 5 4 3 2 1 dcp0 dcp1 spi bus isl22424
18 all intersil u.s. products are m anufactured, assembled and test ed utilizing iso9001 quality systems. intersil corporations quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products , see www.intersil.com fn6425.1 september 9, 2015 about intersil intersil corporation is a leading provider of innovative power management and precision analog solutions. the company's produc ts address some of the largest marke ts within the industrial and i nfrastructure, mobile computing and high-end consumer markets. for the most updated datasheet, application no tes, related documentation and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggesti ons for improving this datashe et by visiting www.intersil.com/ask . reliability reports are also a vailable from our website at www.intersil.com/support. revision history the revision history provided is for informational purposes onl y and is believed to be accurate, but not warranted. please go to the web to make sure that you have the latest revision . date revision change september 9, 2015 fn6425.1 - ordering information table on page 2. - added revision history. - added about intersil verbiage. - updated pod l16.4x4a to lates t revision changes are as follow : updated to new pod format by remo ving table listing dimensions and moving dimensions onto drawing. added typical recommended land pattern. removed package option. - updated pod m14.173 to most cur rent version changes are as fo llow: updated drawing to remove table and added land pattern. isl22424
19 fn6425.1 september 9, 2015 isl22424 package outline drawing l16.4x4a 16 lead quad flat no-lead plastic package rev 3, 03/15 notes: 1. dimensions are in millimeters. dimensions in ( ) for reference only. 2. dimensioning and tolerancing conform to asme y14.5m-1994. 3. unless otherwise specified , tolerance: decimal 0.05 4. dimension applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. tiebar shown (if present) is a non-functional feature. 6. the configuration of the pin #1 identifier is optional, but m ust be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. top view index area (4x) 0.15 pin 1 6 4.00 4.00 a b see typical recommended land pattern 0.20 ref +0.03/-0.02 detail "x" c 5 side view bottom view 0.08 c c seating 0.10 c +0.05 pin #1 5 8 4 0.10 c m 12 9 4 0.50 12x 13 4x 1.50 16 1 6 a b ( 2.40) (12x 0.50) (16x 0.25) (3.8 typ) -0.07 0.25 0.900.10 2.40 16x 0.400.01 (16x 0.60) index area 2.40 detail "x" plane
20 fn6425.1 september 9, 2015 isl22424 package outline drawing m14.173 14 lead thin shrink small outline package (tssop) rev 3, 10/09 detail "x" side view typical recommended land pattern top view b a 17 8 14 c plane seating 0.10 c 0.10 c b a h pin #1 i.d. mark 5.00 0.10 4.40 0.10 0.25 +0.05/-0.06 6.40 0.20 c b a 0.05 0-8 gauge plane see 0.90 +0.15/-0.10 0.60 0.15 0.09-0.20 5 2 3 1 3 1.00 ref 0.65 1.20 max 0.25 0.05 min 0.15 max (1.45) (5.65) (0.65 typ) (0.35 typ) detail "x" 1. dimension does not include mold flash, protrusions or gate b urrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. dimension does not include interlead flash or protrusion. i nterlead flash or protrusion shall not exceed 0.25 per side. 3. dimensions are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m-1994. 5. dimension does not include dambar protrusion. allowable prot rusion shall be 0.80mm total in excess of dimension at maximum materia l condition. minimum space between protrusion and adjacent lead is 0.07mm. 6. dimension in ( ) are for reference only. 7. conforms to jedec mo-153, variation ab-1. notes: end view

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